1. Field of the Invention
The present invention relates to a semiconductor device having fine pattern wiring lines and a related method of manufacture. More particularly, the invention relates to a semiconductor device having fine pattern wiring lines having a fine pitch and contact plugs that respectively connect the wiring lines to an adjacent conductive region, and a related method of manufacture.
2. Description of the Related Art
The fabrication of highly integrated semiconductor devices requires the formation and use of ever more minute patterns and associated elements. That is, in order to integrate the numerous elements forming contemporary semiconductor devices into increasing small areas, the size of individual elements must be reduced and the separation distances between adjacent elements must also be reduced. In part, the reduction in element sizes and increasing density of related elements are enabled by reductions in the “pitch” of the conductive patterns connecting various elements. A pitch is generally defined by the sum of the width of a pattern itself, plus the width of the gap separating the pattern from adjacent patterns or related elements.
The required pitch (or pitches) defining the integration density of contemporary semiconductor devices is largely a product of over-arching design rules for individual semiconductor devices. In many instances, contemporary design rules are mandating pattern pitches that have reached the resolution and performance limits of existing photolithography equipment. For example, resolution restrictions for available photolithography equipment now limit the realizable size of fine pitch contact holes in very small (i.e., narrow) areas of a semiconductor substrate. Such practical limits on the definition and fabrication of contact holes in contemporary semiconductor devices is a function of minimum margins placed on the separation distance and alignment of adjacent contact holes. Existing photolithography resolution limits and restrictions simply can not form contact holes with finer pitches while maintaining acceptable design margins.
One common example of conventional pitch limits being reached may be found in the design and fabrication of adjacent bit lines in semiconductor memory devices. For example, the pitch between bit lines in certain highly integrated flash memory devices has abruptly decreased to a feature size in the range of 30 nm. Available photolithography equipment simply can not be used conventional manner to adequately form such features.
During the formation of “laterally” arranged bit lines in contemporary semiconductor memory devices, respective contact plugs are usually formed to “vertically” connect each bit line to an associated active region or some other element. The terms lateral and vertical are relative in nature and are used to facilitate description. Throughout the description that follows, no arbitrary geometry is mandated by the use of such descriptive terms. After the contact plugs have been formed, the bit lines are formed in electrical contact respective contact plug(s). During this fabrication overlay of laterally running bit lines over an arrangement of previously formed and vertically running contact plugs, certain alignment margins (i.e., tolerance for misalignment between a contact plug and a bit line) must be observed to ensure the reliability of the resulting semiconductor device. Such alignment margins are largely defined by the separation distance that exists between adjacent bit lines and/or contact plugs. Thus, decreasing pitches for bit lines and/or contact plugs will restrict alignment margins